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| 512 K x 32 Static RAM PUMA 68S16000XB - 012/015/017 Issue 5.2 March 2001 Description The PUMA68 range of devices provide a high density surface mount industry standard memory solution which may accommodate various memory technologies including SRAM, EEPROM and FLASH. The devices are designed to offer a defined upgrade path and may be user configured as 8, 16 or 32 bits wide. The PUMA68S16000XB is a 512Kx32 SRAM module housed in a 68 `J' leaded package which complies with the JEDEC 68 PLCC standard. Access times of 12, 15 or 17ns are available. The 5V device is available to commercial and industrial temperature grade. Block Diagram A0~A18 /OE /WE 512K x 8 SRAM 512K x 8 SRAM 512K x 8 SRAM 512K x 8 SRAM /CS1 /CS2 /CS3 /CS4 D0~7 D8~15 D16~23 D24~31 Features * Access times of 12/15/17 ns. * 5V + 10%. * Comercial and Industrial temperature grades * JEDEC standard 68 J Lead footprint. * Industry standard pinout. * May be organised as 512K x 32, 1M x 16, 2M X 8 * Operating Power (32 Bit) 4.18W (max) * Low power standby. (TTL) 1.32W (max) (CMOS) 220mW (max) * Completely Static Operation. Pin Definition See page 2. Pin Functions Description Address Input Data Input/Output Chip Select Write Enable Output Enable No Connect Power Ground Signal A0~A18 D0~D31 /CS1~4 /WE /OE NC VCC VSS Package Details PUMA 68 - Plastic 68 `J' Leaded Package Max. Dimensions- 25.27mm x 25.27mm x 5.08mm Pin Definition - PUMA68S16000XB Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Signal VCC NC /CS1 /CS2 /CS3 /CS4 A17 A18 D16 D17 D18 D19 VSS D20 D21 D22 D23 VCC D24 D25 D26 D27 VSS D28 D29 D30 D31 A6 A5 A4 A3 A2 A1 A0 Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Signal VCC A13 A12 A11 A10 A9 A8 A7 D0 D1 D2 D3 VSS D4 D5 D6 D7 VCC D8 D9 D10 D11 VSS D12 D13 D14 D15 A14 A15 A16 /WE /OE NC NC PAGE 2 Issue 5.2 March 2001 Absolute Maximum Ratings(1) DC Operating Conditions Parameter Voltage on any pin relative to VSS Power Dissipation Storage Temperature Symbol VT PT TSTG Min -0.3 to 4.0 -55 to Max +6.0 Unit V W +125 O C Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability Recommended Operating Conditions Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temperature Symbol VCC VIH VIL TA TAI Notes : (1) Pulse Width : -2.0V for less than 10ns. (1) Min 4.5 2.2 -0.3 0 -40 Typ 5.0 - Max 5.5 VCC+0.5 0.8 70 85 Unit V V V O O C C (I Suffix) DC Electrical Characteristics (VCC=5V+10%, TA=-40OC to +85OC) Parameter Input Leakage Current Output Leakage Current Average Supply Current (2) Symbol Test Condition ILI ILO 32 Bit 16 Bit 8 Bit ICC32 ICC16 ICC8 ISB ISB1 VOL VOH VIN=0V to VCC VI/O=0V to VCC /CS =VIL, II/O=0mA,f=fmax As Above. As Above. /CS =VIH ,Min Cycle /CS>VCC-0.2V, 0.2V >VIN>VCC-0.2V, f=0 IOL=8.0mA, VCC=Min IOH=-4.0mA, VCC=Min (1) (1) Min -8 -8 2.4 Typ - Max 8 8 760 490 370 240 40 0.4 - Unit A A mA mA mA mA mA V V Standby Supply Current TTL CMOS Output Voltage Low Output Voltage High Notes (1) /CS1~4 inputs operate simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode. (2) At f=fMAX address and data inputs are cycling at max frequency. PAGE 3 Issue 5.2 March 2001 Capacitance (VCC = 5.0V, TA = 25OC, F=1MHz.) Parameter Input Capacitance, Address, /OE, /WE Output Capacitance, 8 bit mode (worst case) Note : These Parameters are calculated not measured. Symbol CIN1 CI/O Test Condition VIN=0V VI/O=0V Min - Typ - Max 30 34 Unit pF pF Test Conditions * * * * * * Input pulse levels : 0V to 3.0V Input rise and fall times : 3ns Input and Output timing reference levels : 1.5V Output Load : See Load Diagram. VCC = 5V+10% PUMA module tested in 32 bit mode. Output Load I/O Pin 166 1.76V 30pF Operation Truth Table /CS1 L H H H L H L L H H H L H L X H /CS2 H L H H L H L H L H H L H L X H /CS3 H H L H H L L H H L H H L L X H /CS4 H H H L H L L H H H L H L L X H /OE X X X X X X X L L L L L L L H X /WE L L L L L L L H H H H H H H H X Supply Current ICC8 ICC8 ICC8 ICC8 ICC16 ICC16 ICC32 ICC8 ICC8 ICC8 ICC8 ICC16 ICC16 ICC32 Mode Write D0~D7 Write D8~D15 Write D16~D23 Write D24~D31 Write D0~D15 Write D16~D31 Write D0~D31 Read D0~D7 Read D8~D15 Read D16~D23 Read D24~D31 Read D0~D15 Read D16~D31 Read D0~D31 ICC32 /ICC16/ICC8 D0~D31 High-Z ISB, ISB1 D0~D31 Standby Notes : H=VIH : L=VIL : X=VIH or VIL PAGE 4 Issue 5.2 March 2001 Read Cycle 12 Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Output Hold From Address Change Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to Output in High Z Output Disable to Output in High Z 15 17 AC Operating Conditions Symbol Min Max Min Max Min Max Units tRC tAA tACS tOE tOH tCLZ tOLZ tCHZ tOHZ 12 3 3 0 0 0 12 12 6 6 6 15 3 3 0 0 0 15 15 7 7 7 17 3 3 0 0 0 17 17 8 8 8 ns ns ns ns ns ns ns ns ns Write Cycle 12 Parameter Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width (/OE High) Write Pulse Width (/OE Low) Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold time from Write Time Output Active from End of Write Symbol tWC tCW tAW tAS tWP1 tWP2 tWR tWHZ tDW tDH tOW 15 17 Units ns ns ns ns ns ns ns ns ns ns ns Min Max Min Max Min Max 12 8 8 0 8 12 0 0 6 0 3 6 15 10 10 0 10 12 0 0 7 0 3 7 17 12 12 0 12 13 0 0 8 0 3 8 - PAGE 5 Issue 5.2 March 2001 Read Cycle 1 (Address Controlled, /CS=/OE=VIL, /WE=VIH) tRC Address tOH Data Out Previous Data Valid tAA Data Valid Timing Waveforms Read Cycle 2 (/WE = VIH) tRC Address tAA tACS /CS tOHZ tOE /OE tOLZ tCLZ(4,5) Data Out Valid Data tOH tCHZ(3,4,5) NOTES(READ CYCLE) 1. /WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or VOL levels. 4. At any given temperature and voltage condition, t CHZ(Max.) is less than t CLZ(Min.) both for a given device and from device to device. 5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with /CS=V IL. 7. Address valid prior to coincident with /CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 9. /CS=/CS1~4 PAGE 6 Issue 5.2 March 2001 Write Cycle 1 (/OE = Clock) tWC Address tAW /OE tCW(3) /CS tWR(5) tAS(4) /WE tWP(2) tDW High Z Data In tOHZ(6) High Z(8) Data Out Valid Data tDH NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 6. If OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. 11 ./CS=/CS1~4 PAGE 7 Issue 5.2 March 2001 Write Cycle 2 (/OE = Low Fixed) tWC Address tAW tCW(3) /CS tAS(4) /WE tDW High Z Data In tWHZ(6) High Z(8) Data Out Valid Data tOW (10) (9) tDH tWP(2) tWR(5) NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 6. If OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. 11 ./CS=/CS1~4 PAGE 8 Issue 5.2 March 2001 Write Cycle 3 (/CS = Controlled) tWC Address tAW tCW(3) /CS tAS(4) /WE tDW High Z Data In tLZ High Z Data Out tWHZ(6) High Z(8) Valid Data tDH High Z tWP(2) tWR(5) NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. t WP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. t WR applied in case a write ends as /CS or /WE going high. 6. If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. 11 /CS=/CS1~4 PAGE 9 Issue 5.2 March 2001 Package Details PUMA 68 Pin JEDEC Surface Mount PLCC 25.27 (0.995) 25.02 (0.985) Pin 1 Pin 68 XXXXXX-X 5.08 (0. 200) max 0.46 (0. 018) 23.11 (0.910) 24.13 (0.950) 1.27 (0. 050) 0.90 (0. 035) typ Notes: 1. All dimensions in mm (inches). PAGE 10 Issue 5.2 March 2001 Ordering Information Ordering Information PUMA 68S16000XBI - 015 Speed 012 = 12ns 015 = 15ns 017 = 17ns Temp. Range/ScreeningBlank = Commercial I = Industrial Pinout Configuration XB = Chip Scale BGA Based Design, Industry Standard Pinout 16000 = 512K x 32 configurable as 1M x 16 and 2M x 8 S = SRAM PUMA 68 = 68 pin `J' Leaded PLCC Memory Organisation Technology Package Note : Although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. Our products are subject to a constant process of development. Data may be changed without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director. PAGE 11 Issue 5.2 March 2001 Customer Guidelines Moisture Sensitivity Devices are moisture sensitive. Shelf Life in Sealed Bag 12 months at <40OC and <90% relative humidity (RH). After this bag has been opened, devices that will be subjected to infrared reflow, vapour phase reflow, or equivalent processing (peak package body temp 220OC) must be : A : Mounted within 72 Hours at factory conditions of <30OC/60% RH OR B : Stored at <20% RH If these conditions are not met or indicator card is >20% when read at 23OC +/-5% devices require baking as specified below. If baking is required, devices may be baked for :A : 24 hours at 125OC +/-5% for high temperature device containers OR B : 192 hours at 40OC +5OC/-0OC and <5% RH for low temperature device containers. Packaging Standard Packaged in trays as standard. Tape and reel available for shipment quantities exceeding 200pcs upon request. Soldering Recomendations IR/Convection Ramp Rate Temp. exceeding 183OC Peak Temperature Time within 5OC of peak Ramp down Ramp up rate Peak Temperature Time within 5OC of peak Ramp down 6OC/sec max. 150 secs. max. 225OC 20 secs max. 6OC/sec max. 6OC/sec max. 215 - 219OC 60 secs max. 6OC/sec max. Vapour Phase - Note : The above recomendations are based on standard industry practice. Failiure to comply with the above recomendations invalidates product warranty. PAGE 12 Issue 5.1 April 2000 |
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